Single-Grain Si TFTs and Circuits Inside Location-Controlled Grains Fabricated Using a Capping Layer of \hbox

• Published in: IEEE transactions on electron devices Vol. 54; no. 1; pp. 124 - 130
• Main Authors: Rana, Vikas, Ishihara, Ryoichi, Hiroshima, Yasushi, Inoue, Satoshi, Shimoda, Tatsuya, Metselaar, Wim, Beenakker, Kees
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2007
• Subjects: Capping layer (C/L) of hbox{SiO}_{2}; CMOS inverter; Crystallization; excimer laser; Grain size; Inverters; Lasers; location control; Logic gates; Silicon; Thin film transistors; thin-film transistor (TFT)
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2006.887516

To enlarge the size of two-dimensional location-controlled Si grains fabricated in the mu-Czochralski process in excimer-laser crystallization, a capping layer (C/L) of SiO 2 was applied to the amorphous-Si (a-Si) thin film. With a 50-nm-thick SiO 2 C/L on a 100-nm-thick a-Si film, the diameter of the location-controlled grain was increased to 7.5 mum. Single-grain Si thin-film transistors (TFTs) were fabricated with the SiO 2 C/L as part of the gate insulator. Field-effect mobilities of 510 and 210 cm 2 /Vmiddots were obtained for electrons and holes, respectively. Both TFTs were integrated in a single-grain CMOS inverter inside a location-controlled grain. The propagation gate delay was found to be shorter than that in poly-Si circuits under the same device conditions