A two stage pipeline architecture for hardware implementation of multi-level decomposition of 1-D framelet transform

• Published in: Microprocessors and microsystems Vol. 108; p. 105064
• Main Authors: Kumar, Kasetty Praveen, Kanhe, Aniruddha
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.07.2024
• Subjects: Discrete framelet transform; FIR filter; FPGA; Pipeline architecture; Symmetric/anti-symmetric extension; FIR filter; Pipeline architecture; FPGA; Discrete framelet transform; Symmetric/anti-symmetric extension
• ISSN: 0141-9331; 1872-9436
• DOI: 10.1016/j.micpro.2024.105064

In this paper a two stage pipeline architecture for computation of multilevel decomposition of framelet transform is proposed. To handle the problem of perfect reconstruction, an area efficient symmetric extension router is used that duplicates the appropriate number of data samples of input signal at the boundary followed by reflection about the symmetry axis. In addition, to reduce the period and number of clock cycles required for computing the framelet transform, the inter-stage and intrastage pipeline of the computational units is maximized. The inter-stage pipelining is obtained by distributing the various levels of decomposition among the computational units of two stages, and a synchronization mechanism is adopted to reduce the total number of clock cycles. Similarly, the intrastage pipelining is achieved by using the pipeline registers such that the clock period is limited to the delay of multiplier and accumulator (MAC) circuit of the finite-impulse response (FIR) filter. To validate the feasibility and functionality of the proposed hardware architecture, the design is implemented on Artix7 XC7A100TCSG324-1 field-programmable gate array (FPGA) for the case of framelet transform with one low-pass and two high-pass filters. The proposed architecture is able to operate at a maximum clock frequency of 112 MHz.