Global optimization of multipleiers and buses in interconnect synthesis

• Published in: Microelectronics Vol. 24; no. 5; pp. 513 - 532
• Main Authors: Wilson, T.C., Halley, B., Banerji, D.K., Garg, M.K., Deadman, R.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.08.1993
• ISSN: 1879-2391; 1879-2391
• DOI: 10.1016/0026-2692(93)90120-4

In this paper, we consider the problem of optimizing interconnection complexity in behavioral level synthesis of digital systems. We assume that, as a result of other steps in synthesis, logical connection requirements have already been determined, with a corresponding level of multiplexing implied. We further reduce the total amount of multiplexing by combining logical connections into shared (physical) connections wherever possible. Our measure of interconnection complexity is the number of equivalent 2×1 multiplexers. Using this criterion, we can guarantee an optimal solution to this problem. The problem is modelled with a graph, which is then pruned extensively before being used as an input to any one of the two alternative solution techniques. The primary (and optimum) technique employs integer linear programming. We also provide a faster heuristic solution that yields near-optimal results. Since the actual implementation of shared connections may vary widely, we also show how the linear program can be modified to optimize and count the total number of n×1 multiplexers (n⩾2) or the total number of tri-state buffers in a bus-based interconnect implementation.