Design of Fused Add-Multiply Operator using Modified Booth Recoder for Fast Arithmetic Circuits
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| Published in | Indian journal of science and technology Vol. 8; no. 19 |
|---|---|
| Main Authors | , |
| Format | Journal Article |
| Language | English |
| Published |
14.08.2015
|
| Online Access | Get full text |
| ISSN | 0974-6846 0974-5645 |
| DOI | 10.17485/ijst/2015/v8i19/77052 |
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| Author | Raghavendra, Jonnalagadda Vigneswaran, T. |
|---|---|
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| Title | Design of Fused Add-Multiply Operator using Modified Booth Recoder for Fast Arithmetic Circuits |
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