Multi-microprocessor architecture for the LEP storage ring controls

• Published in: IFAC Proceedings Volumes Vol. 18; no. 1; pp. 55 - 61
• Main Authors: Altaber, J., Innocenti, P.G., Rausch, R.
• Format: Journal Article
• Language: English
• Published: 01.05.1985
• Subjects: accelerator control; distributed arbitration; function-to-function architecture; message passing protocol; Multi-microprocessor architecture; VME multiprocessor; function-to-function architecture; accelerator control; VME multiprocessor; Multi-microprocessor architecture; message passing protocol; distributed arbitration
• ISSN: 1474-6670
• DOI: 10.1016/B978-0-08-031664-2.50015-2

The new CERN Large Electron Positron (LEP) storage ring control system follows the concepts developed for the Super Proton Synchrotron (SPS) accelerator but making use of present day technology. A multi-tasking computer is replaced by an assembly of microprocessor based modules performing a unique, single stream type of task. Each module is a general purpose processing unit (GPU) containing a 68000 microprocessor, private memory, protected memory accessible by others GPU's, a programmable and adressable interrupt logic and a distributed arbitration mechanism. Communication amongst GPU's is done by a message protocol, the medium being the VME multi-master parallel bus. Dedicated Input/Output modules can be associated privately with the GPU's thus forming specialized functional modules, or providing additional private memory. All these functional modules communicate over the VMEbus in a protected access mode with resource reservation to prevent processor interferences. A global system concept has been developed which will be detailed in this paper. The improvement in performance, flexibility, processor independence, minimization of integration effort required, as well as error diagnostics in such a multiprocessor architecture are also discussed.