An Ultra-Fast 460-mA Capacitorless DLDO Achieving 8-ns Recovery Time and 99.58% Current Efficiency

• Published in: Journal of semiconductor technology and science Vol. 25; no. 1; pp. 94 - 101
• Main Authors: Wahla, Ibrar Ali, Akram, Muhammad Abrar, Hwang, In-Chul
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.02.2025
• Subjects: 전기공학
• ISSN: 2233-4866; 1598-1657; 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2025.25.1.94

In this brief, a fully-integrated output-capacitorless digital low-dropout regulator (DLDO) is proposed utilizing the parallel proportional and integral (PI) controllers to achieve reduced voltage undershoot (∆VREG) and fast transient response time (TREC). The proposed PI controllers are implemented with the self-shifting bidirectional shift registers (SS-SRs) in coarse-fine dual loops along with complimentary PMOS and NMOS power transistors in coarse switch array and small-sized PMOS only transistors in fine switch array. Complimentary connections of PMOS and NMOS power transistors compensate for the load current (ILOAD) to reduce the ∆VREG, and smallsized PMOS reduces the steady-state voltage ripples. The proposed DLDO was designed and fabricated in a 65-nm CMOS process with an active area of 0.08 mm2 . Simulated results demonstrate that the proposed capacitor-less DLDO operates with an input voltage range of 0.7 V-1.2 V. For a load current step of 460 mA at VDD = 1.2 V, the proposed DLDO recovers a ∆VREG of 74 mV within 8 ns achieving an efficient load regulation of 0.004 mV/mA with a peak current efficiency of 99.58 %. KCI Citation Count: 0