Dielectric and Interface Properties of TiO2/HfSiO/SiO2 Layered Structures Fabricated by in situ PVD Method

• Published in: ECS transactions Vol. 16; no. 5; pp. 121 - 129
• Main Authors: Arimura, Hiroaki, Naitou, Yuichi, Kitano, Naomu, Oku, Yudai, Yamaguchi, Nobuo, Kosuda, Motomu, Hosoi, Takuji, Shimura, Takayoshi, Watanabe, Heiji
• Format: Journal Article
• Language: English
• Published: 03.10.2008
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/1.2981593

We proposed TiO2/HfSiO/SiO2 layered gate dielectrics and demonstrated the use of the layered structure for scaling equivalent oxide thickness (EOT) and reducing gate leakage current (Jg). Ti diffusion into the HfSiO/SiO2 underlayers, during Ti oxidation annealing for forming TiO2 caps on HfSiO/SiO2, was found to increase leakage current, positive fixed charges, interface state density, and additional charge traps after applying bias stress. By using low temperature Ti-oxidation annealing and forming gas annealing (FGA) treatment, we successfully controlled Ti diffusion and terminated Ti-induced defects. We achieved excellent EOT-Jg characteristics (EOT = 0.71 nm, Jg = 7.2 x 10-2 A/cm2), which are equal to the leakage merit of over five orders of magnitude compared with conventional poly-Si/SiO2/Si gate stacks, while maintaining a superior interface property (interface trap density: Dit = 9.9 x 1010 eV-1cm-2).