Sub-10-nm Diameter Vertical Nanowire p-Type GaSb/InAsSb Tunnel FETs

• Published in: IEEE electron device letters Vol. 43; no. 6; pp. 846 - 849
• Main Authors: Shao, Yanjie, del Alamo, Jesus A.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: digital etch; Gallium antimonides; GaSb; Heterojunctions; Heterostructures; III-Vs; InAsSb; Logic gates; Nanowires; Performance evaluation; Room temperature; TFETs; Three-dimensional displays; top-down; Transconductance; Tunnel FETs; Tunneling; Tunnels
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2022.3166846

In this letter, we report the realization of sub-10-nm diameter vertical nanowire (VNW) p-type tunnel FETs (TFETs). Using a broken-band GaSb/InAsSb heterostructure design and a top-down fabrication approach, we demonstrate a 9-nm diameter VNW TFET with excellent on-state characteristics featuring a peak transconductance of 90 <inline-formula> <tex-math notation="LaTeX">\mu \text{S}/\mu \text{m} </tex-math></inline-formula> at <inline-formula> <tex-math notation="LaTeX">V_{{\text {ds}}} = -0.3 </tex-math></inline-formula> V. The same device exhibits a minimum linear subthreshold swing of 225 mV/dec at <inline-formula> <tex-math notation="LaTeX">V_{\text {ds}} = -0.05 </tex-math></inline-formula> V. Our p-type GaSb/InAsSb TFETs exhibit clear negative differential resistance at room temperature, with a peak-to-valley current ratio over 3. The excellent device performance of these devices bodes well for the viability of GaSb-based complementary TFETs in future ultra-scaled logic technologies.