A 1.5 V 20 kHz 108.07 dB SNR discrete-time dynamic zoom ADC based on ultra low leakage process

Abstract This study introduces a hybrid discrete-time (DT) dynamic Zoom ADC based on the CanSemi 110-nm Mixed Signal CMOS process. The two-step conversion process, comprising parallel coarse and fine phases, is executed by a 5-bit asynchronous SAR ADC and a third-order ΣΔ modulator. Non-ideal effect...

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Bibliographic Details
Published inJournal of physics. Conference series Vol. 2810; no. 1; pp. 12012 - 12024
Main Authors Liu, Hengzhi, Xu, Fei, Kit Kwan, Hing, Wu, Zhaohui, Li, Bin
Format Journal Article
LanguageEnglish
Published Bristol IOP Publishing 01.07.2024
Subjects
Circuits
Constraint modelling
Noise levels
Operational amplifiers
Signal processing
Signal to noise ratio
Threshold voltage
Transconductance
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Summary:Abstract This study introduces a hybrid discrete-time (DT) dynamic Zoom ADC based on the CanSemi 110-nm Mixed Signal CMOS process. The two-step conversion process, comprising parallel coarse and fine phases, is executed by a 5-bit asynchronous SAR ADC and a third-order ΣΔ modulator. Non-ideal effects present in Zoom ADC were analysed and quantified through modelling, deriving design specifications of circuits. Under the constraints of low power supply and high threshold voltages, boost circuits were implemented to counteract the MOS switch-on-resistance nonlinearity. The Operational Transconductance Amplifier (OTA) in the integrators adopts a folded cascode structure. Data Weighted Averaging (DWA) and Chopper-Stabilization (CHS) techniques were employed to alleviate the effects of capacitor mismatch and offset. The post-simulation results indicate the proposed Zoom ADC achieved 108.07 dB Signal-to-Noise Ratio (SNR) over a 20 kHz bandwidth while utilizing 3.32 mW of power.
ISSN:1742-6588
1742-6596
DOI:10.1088/1742-6596/2810/1/012012