FPGA PLACEMENT OPTIMIZATION BY TWO-STEP UNIFIED GENETIC ALGORITHM AND SIMULATED ANNEALING ALGORITHM

• Published in: Journal of electronics (China) Vol. 23; no. 4; pp. 632 - 636
• Main Authors: Yang, Meng, Almaini, A. E. A., Wang, Pengjun
• Format: Journal Article
• Language: English
• Published: School of Engineering, Napier University, 10 Colinton Road, Edinburgh, EH10 5DT, UK 01.07.2006; State Key Lab of ASIC & System, Microelectronics Dept, Fudan University, Shanghai 201203, China%School of Engineering, Napier University, 10 Colinton Road, Edinburgh, EH10 5DT, UK%Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China
• Subjects: 优化算法; 模拟退火; 路由设备; 遗传算法; Genetic Algorithm (GA); EDA; Placement; FPGA; Simulated Annealing (SA)
• ISSN: 0217-9822; 1993-0615
• DOI: 10.1007/s11767-005-0198-3

Genetic Algorithm （GA） is a biologically inspired technique and widely used to solve numerous combinational optimization problems. It works on a population of individuals, not just one single solution. As a result, it avoids converging to the local optimum. However, it takes too much CPU time in the late process of GA. On the other hand, in the late process Simulated Annealing （SA） converges faster than GA but it is easily trapped to local optimum. In this letter, a useful method that unifies GA and SA is introduced, which utilizes the advantage of the global search ability of GA and fast convergence of SA. The experimental results show that the proposed algorithm outperforms GA in terms of CPU time without degradation of performance. It also achieves highly comparable placement cost compared to the state-of-the-art results obtained by Versatile Place and Route （VPR） Tool.