Experimental /} Invariance Assessment for Asymmetric Double-Gate FDSOI MOSFET

Transconductance efficiency (<inline-formula> <tex-math notation="LaTeX">{g}_{m}/{I}_{D} </tex-math></inline-formula>) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of <inline-formula> <tex-mat...

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Published inIEEE transactions on electron devices Vol. 65; no. 1; pp. 11 - 18
Main Authors El Ghouli, Salim, Rideau, Denis, Monsieur, Frederic, Scheer, Patrick, Gouget, Gilles, Juge, Andre, Poiroux, Thierry, Sallese, Jean-Michel, Lallement, Christophe
Format Journal Article
LanguageEnglish
Published IEEE 01.01.2018
Subjects
Analog and RF
double-gate (DG) FETs
fully depleted Silicon-on-Insulator (FDSOI)
Logic gates
low power
MOSFET
Semiconductor device modeling
Silicon
Silicon-on-insulator
Transconductance
transconductance efficiency
ultrathin body and box (UTBB)
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Summary:Transconductance efficiency (<inline-formula> <tex-math notation="LaTeX">{g}_{m}/{I}_{D} </tex-math></inline-formula>) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of <inline-formula> <tex-math notation="LaTeX">{g}_{m}/{I}_{D} </tex-math></inline-formula> versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the <inline-formula> <tex-math notation="LaTeX">{g}_{m}/{I}_{D} </tex-math></inline-formula>-based design methodologies usage in DG FDSOI transistors sizing.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2017.2772804