Program Pulse Control for Program Efficiency and Disturbance of 3D-NAND Flash Using Novel Machine Learning-Based Pareto Optimization

• Published in: IEEE transactions on electron devices Vol. 71; no. 11; pp. 6713 - 6718
• Main Authors: Nam, Kihoon, Kim, Donghyun, Yun, Hyeok, Park, Chanyang, Jang, Hyundong, Cho, Kyeongrae, Eom, Seungjoon, Kim, Jiyoon, Lee, Seonhaeng, Lee, Namhyun, Kim, Gang-Jun, Baek, Rock-Hyun
• Format: Journal Article
• Language: English
• Published: IEEE 01.11.2024
• Subjects: 3D-NAND; Logic gates; Machine learning; machine learning (ML); Mathematical models; optimization framework; Pareto front; Pareto optimization; program pulse (PP); Semiconductor device modeling; Shape; Simulation; Threshold voltage; Training; Tunneling
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2024.3469186

We propose a novel approach that combines machine learning (ML) and Pareto optimization to simultaneously enhance the program efficiency and disturbance of 3D-NAND flash memory. The relationship between program pulse (PP) shapes and threshold voltage shifts has never been investigated owing to the presence of numerous PP shapes. The complex relationship is modeled rapidly and quantitatively by leveraging ML. A multiobjective optimization problem is designed to consider the trade-off in program efficiency and disturbance. Pareto optimization facilitates determining PP shapes that achieve optimal solutions between maximizing program efficiency and minimizing program disturbance. The Pareto front provides practical and intuitive candidates for determining optimal PP shapes. Experimental results confirm that the program efficiency and disturbance can be enhanced by 14%-22% and 5%-40%, respectively. The ML-based Pareto optimization has the potential to vary the pulse conditions for desired operations in 3D-NAND flash, which is the biggest nonvolatile memory market in the semiconductor industry.