Reliability of deep submicron MOSFETs

In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradations are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, de...

Full description

Saved in:
Bibliographic Details
Published inJournal of Telecommunications and Information Technology no. 1
Main Author Francis Balestra
Format Journal Article
LanguageEnglish
Published National Institute of Telecommunications 30.03.2001
Subjects
bulk MOSFETs
deep submicron transistors
reliability
SOI devices
Online AccessGet full text

Cover

More Information
Summary:In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradations are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, device lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined.
ISSN:1509-4553
1899-8852
DOI:10.26636/jtit.2001.1.48