Impact of µA-ON-Current Gate-All-Around TFT (GAT) for Static RAM of 16Mb and beyond

• Published in: Japanese Journal of Applied Physics Vol. 35; no. 2S; p. 910
• Main Authors: Maegawa, Shigeto, Ipposhi, Takashi, Maeda, Shigenobu, Kuriyama, Hirotada, Kohno, Yoshio, Inoue, Yasuo, Hirokazu Miyoshi, Hirokazu Miyoshi, Tadashi Hirao, Tadashi Hirao
• Format: Journal Article
• Language: English
• Published: 01.02.1996
• ISSN: 0021-4922; 1347-4065
• DOI: 10.1143/JJAP.35.910

The gate-all-around thin-film transistor (TFT) (GAT) with thin channel poly-Si can suppress the individual performance variation induced by a poly-Si grain boundary in the channel, in addition to improving the average performance compared to the conventional single-gate TFT (SGT). This effect is attributed to the thinning of the effective channel poly-Si by half in the GAT. Poly-Si TFT simulation results clearly confirmed this effect in terms of the current( I )-voltage( V ) characteristics and channel potential. The GAT also reduces the threshold voltage instability under negative bias temperature (-BT) stress because the GAT structure relaxes the stress electric field in the gate oxide. The high-performance GAT enables reduction of the size of the static random access memory (SRAM) cell by providing a large ON-current to the storage node and enhancing the data retention stability despite the low cell ratio. The GAT-SRAM cell is a strong candidate for SRAM of 16 Mb and beyond.