A Comprehensive Comparison of Different Wafer/Channel Orientations for Ultrascaled Nanosheet FETs

In this article, we evaluate various crystal orientation configurations for silicon ultrascaled nanosheet FETs (NSFETs) to explore the optimum combination of wafer surface and channel orientations. The increasingly prominent physical phenomena, including quantum confinement and quasi-ballistic trans...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 71; no. 3; pp. 1784 - 1791
Main Authors Zhao, Yusi, Xu, Zhongshan, Ding, Rongzheng, Zhao, Yage, Yu, Shaofeng
Format Journal Article
LanguageEnglish
Published New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.03.2024
Subjects
Carrier density
CMOS
Configurations
Crystal structure
Crystallography
Inverters
Nanosheets
Quantum confinement
Transport properties
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Summary:In this article, we evaluate various crystal orientation configurations for silicon ultrascaled nanosheet FETs (NSFETs) to explore the optimum combination of wafer surface and channel orientations. The increasingly prominent physical phenomena, including quantum confinement and quasi-ballistic transport, are captured physically by advanced simulation methodology. The carrier density profile and transport-related parameters exhibit a strong dependence on the crystallographic orientations of the channel and the wafer directions. The quantum confinement effects are least pronounced in the n-type NSFETs with a (100) surface, and the p-type NSFETs with a (110) surface. The [Formula Omitted] and [Formula Omitted] channel orientations demonstrate the largest ballistic injection velocity for electrons and holes, respectively. Uniaxial stress technology, as an efficient performance booster, may further improve the transport properties, but the enhancement may saturate at high stress level. In the ballistic limit, we predict that the homo-oriented CMOS inverter of [Formula Omitted] configuration has a more balanced N/P current, and the hetero-oriented CMOS inverter, comprising a [Formula Omitted] nm n-type NSFET of [Formula Omitted] and a [Formula Omitted] nm p-type NSFET of [Formula Omitted], will yield a speed enhancement exceeding 20% when compared with the prevailing industry standard of the [Formula Omitted] configuration.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2024.3358790