Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

• Published in: 2010 International Electron Devices Meeting pp. 11.7.1 - 11.7.3
• Main Authors: Pawlak, M A, Popovici, M, Swerts, J, Tomida, K, Min-Soo Kim, Kaczer, B, Opsomer, K, Schaekers, M, Favia, P, Bender, H, Vrancken, C, Govoreanu, B, Demeurisse, C, Wan-Chih Wang, Afanas'ev, V V, Debusschere, I, Altimime, L, Kittl, J A
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Annealing; Crystallization; Oxidation; Random access memory; Strontium; Tin
• ISBN: 9781442474185; 1442474181
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2010.5703344

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO x interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10 -6 A/cm 2 (10 -8 A/cm 2 ) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (>; 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.