A Sub-mW Fractional- ADPLL With FOM of −246 dB for IoT Applications

• Published in: IEEE journal of solid-state circuits Vol. 53; no. 12; pp. 3540 - 3552
• Main Authors: Liu, Hanli, Tang, Dexian, Sun, Zheng, Deng, Wei, Ngo, Huy Cu, Okada, Kenichi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.12.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital phase-locked loop (ADPLL); Amplification; Bluetooth; bluetooth low energy (BLE); Calibration; constant-slope; Converters; Delays; digital PLL; digital-to-time converter (DTC); DPLL; fast lock; Figure of merit; FOM; fractional-<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">N; frequency synthesizer; gain calibration; Internet of Things; Internet-of-Things (IoT); Jitter; Linearity; MOS devices; Phase locked loops; phase-locked loops (PLLs); Power consumption; Power demand; sub-mW; time amplifier (TA); time-to-digital converter (TDC); ultralow power (ULP); Vibration
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2018.2878836

This paper presents a sub-mW fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 <inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula> at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional-<inline-formula> <tex-math notation="LaTeX">{N} </tex-math></inline-formula> ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.