1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in 0.13~\mu \text CMOS

• Published in: IEEE transactions on circuits and systems. I, Regular papers Vol. 65; no. 1; pp. 39 - 50
• Main Authors: Bayram, Erkan, Aref, Ahmed Farouk, Saeed, Mohamed, Negra, Renato
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.01.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: All-digital delay-locked loop (ADDLL); Clocks; CMOS; dead-zone free; Delay lines; Delays; Detectors; Flip-flops; Frequency ranges; Jitter; Locking; low jitter; low power; Phase detectors; Power demand; Radiation detectors; Sensors; small area; Vibration; wide range
• ISSN: 1549-8328; 1558-0806
• DOI: 10.1109/TCSI.2017.2715899

A 1.5-3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm 2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.