In-Memory Computing with Memristor Arrays

• Published in: 2018 IEEE International Memory Workshop (IMW) pp. 1 - 4
• Main Authors: Can Li, Belkin, Daniel, Yunning Li, Peng Yan, Miao Hu, Ning Ge, Hao Jiang, Montgomery, Eric, Peng Lin, Zhongrui Wang, Strachan, John Paul, Barnell, Mark, Qing Wu, Williams, R. Stanley, Yang, J. Joshua, Qiangfei Xia
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2018
• Subjects: Biological neural networks; Computer architecture; Memristors; Resistance; Training; Transistors; Tumors
• ISSN: 2573-7503
• DOI: 10.1109/IMW.2018.8388838

Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO 2 memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.