1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

• Published in: IEEE electron device letters Vol. 23; no. 10; pp. 621 - 623
• Main Authors: Rengarajan, R., Boyong He, Ransom, C., Chang Ju Choi, Ramachandran, R., Haining Yang, Butt, S., Halle, S., Yan, W., Lee, K., Chudzik, M., Robl, W., Parks, C., Massey, J.G., La Rosa, G., Yujun Li, Radens, C., Divakaruni, R., Crabbe, E.
• Format: Journal Article
• Language: English
• Published: IEEE 01.10.2002
• Subjects: CMOS technology; DRAM chips; Hot carriers; Microelectronics; MOS devices; Random access memory; Research and development; Scalability; Silicon
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2002.803854

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V DD Of 1.5-V and 25/spl deg/C, drive currents of 634 μA/μm for 90-nm L/sub gate/ NMOS and 208 μA-μm for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA/μm off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.