Comparison of bulk and SOI CMOS technologies in a DSP processor circuit implementation

• Published in: ICM 2001 Proceedings. The 13th International Conference on Microelectronics pp. 107 - 110
• Main Authors: Simonen, P., Heinonen, A., Kuulusa, M., Nurmi, J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: CMOS digital integrated circuits; CMOS process; CMOS technology; Digital integrated circuits; Digital signal processing; Digital signal processing chips; Energy consumption; Integrated circuit technology; Silicon on insulator technology; Voltage
• ISBN: 9780780375222; 078037522X
• DOI: 10.1109/ICM.2001.997499

Silicon-on-insulator (SOI) CMOS technologies are very attractive options for implementing high-speed digital integrated circuits for low-power applications. This paper presents the layout migration of a DSP processor chip from a 0.6 /spl mu/m bulk CMOS to a 0.5 /spl mu/m SOI CMOS technology. The layout migration and verification are described and the two CMOS designs are compared using two main criteria: circuit speed and average power consumption. For nominal supply voltages, the simulations suggest that the SOI circuit can operate at a speed of 98 MHz which is 51 % higher than that of the original (65 MHz). The average power consumption is 35 % lower in the SOI circuit by using 3.3 V and 35 MHz for both SOI and bulk CMOS designs.