Trading Accuracy for Power with an Underdesigned Multiplier Architecture

We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2×2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% - 45.4% over corresponding accurate multiplier designs, for an average error of 1.39% - 3.32%....

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Bibliographic Details
Published in2011 24th Internatioal Conference on VLSI Design pp. 346 - 351
Main Authors Kulkarni, P, Gupta, P, Ercegovac, M
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2011
Subjects
Adders
Computer architecture
Hardware
Runtime
Signal to noise ratio
Software
Transform coding
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Summary:We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2×2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% - 45.4% over corresponding accurate multiplier designs, for an average error of 1.39% - 3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design-dependent. We compare this circuit-centric approach to power-quality tradeoffs with a pure software adaptation approach for a JPEG example. We also enhance the design to allow for correct operation of the multiplier using a residual adder, for non error-resilient applications.
ISBN:1612843271
9781612843278
ISSN:1063-9667
2380-6923
DOI:10.1109/VLSID.2011.51