Secure Beamforming Design for IRS-ISAC Systems With a Hardware-Efficient Hybrid Beamforming Architecture

• Published in: IEEE transactions on vehicular technology Vol. 74; no. 8; pp. 12160 - 12174
• Main Authors: Xiong, Weijie, Zhao, Zhenglan, Lin, Jingran, Xiao, Zhiling, Li, Qiang
• Format: Journal Article
• Language: English
• Published: IEEE 01.08.2025
• Subjects: Array signal processing; communication security; Costs; Eavesdropping; Hardware; hybrid beamforming; Integrated sensing and communication; integrated sensing and communication (ISAC); Intelligent reflecting surface (IRS); non-convex optimization; Radar; Radio frequency; Reflection coefficient; Signal to noise ratio; Vectors
• ISSN: 0018-9545; 1939-9359
• DOI: 10.1109/TVT.2025.3550387

In this paper, we employ a hardware-efficient hybrid beamforming (HB) architecture to achieve balanced performance in an intelligent reflecting surface (IRS)-assisted integrated sensing and communication (ISAC) system. We consider a scenario where a multi-antenna, dual-function base station (BS) performs secure beamforming for a multi-antenna legitimate receiver while simultaneously detecting potential targets. Our objective is to maximize the communication secrecy gap by jointly optimizing the analog and digital beamformers, IRS reflection coefficients, and radar scaling factor, subject to constraints on beampattern similarity, total transmit power budget, and the constant modulus of both the analog beamformer and IRS reflection coefficients. This secrecy gap maximization problem is generally non-convex. To address this, we incorporate the exterior penalty method by adding the radar constraint as a penalty term in the objective function. We then propose an efficient approach based on the penalty dual decomposition (PDD) framework to solve the reformulated problem, featuring closed-form solutions at each step and guaranteeing convergence to a stationary point. Simulation results validate the effectiveness of the proposed algorithm and demonstrate the superiority of the IRS-ISAC system with HB architecture in balancing performance and hardware costs.