Evaluating the effect of last-level cache sharing on integrated GPU-CPU systems with heterogeneous applications

• Published in: 2016 IEEE International Symposium on Workload Characterization (IISWC) pp. 1 - 10
• Main Authors: Garcıa, Vıctor, Gomez-Luna, Juan, Grass, Thomas, Rico, Alejandro, Ayguade, Eduard, Pena, Antonio J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2016
• Subjects: Benchmark testing; Central Processing Unit; Coherence; Computational modeling; Computer architecture; Graphics processing units; Synchronization
• DOI: 10.1109/IISWC.2016.7581277

Heterogeneous systems are ubiquitous in the field of High- Performance Computing (HPC). Graphics processing units (GPUs) are widely used as accelerators for their enormous computing potential and energy efficiency; furthermore, on-die integration of GPUs and general-purpose cores (CPUs) enables unified virtual address spaces and seamless sharing of data structures, improving programmability and softening the entry barrier for heterogeneous programming. Although on-die GPU integration seems to be the trend among the major microprocessor manufacturers, there are still many open questions regarding the architectural design of these systems. This paper is a step forward towards understanding the effect of on-chip resource sharing between GPU and CPU cores, and in particular, of the impact of last-level cache (LLC) sharing in heterogeneous computations. To this end, we analyze the behavior of a variety of heterogeneous GPU-CPU benchmarks on different cache configurations. We perform an evaluation of the popular Rodinia benchmark suite modified to leverage the unified memory address space. We find such GPGPU workloads to be mostly insensitive to changes in the cache hierarchy due to the limited interaction and data sharing between GPU and CPU. We then evaluate a set of heterogeneous benchmarks specifically designed to take advantage of the finegrained data sharing and low-overhead synchronization between GPU and CPU cores that these integrated architectures enable. We show how these algorithms are more sensitive to the design of the cache hierarchy, and find that when GPU and CPU share the LLC execution times are reduced by 25% on average, and energy-to-solution by over 20% for all benchmarks.