Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

• Published in: International journal of electrical and computer engineering (Malacca, Malacca) Vol. 9; no. 1; p. 148
• Main Authors: Ismael, Sarmad, Tareq, Omar, Qassim, Yahya Taher
• Format: Journal Article
• Language: English
• Published: Yogyakarta IAES Institute of Advanced Engineering and Science 01.02.2019
• Subjects: Algorithms; Basic converters; Co-design; Field programmable gate arrays; Mathematical analysis; Segments
• ISSN: 2088-8708; 2088-8708
• DOI: 10.11591/ijece.v9i1.pp148-156

Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).