A 20 K CMOS array with 200-ps gate delay

A 20 K NAND2 equivalent CMOS gate array prototype with 0.5- mu m channel length FETs is described. The 7.5*7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128*8 SRAM (static random-access memory) h...

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Bibliographic Details
Published inIEEE journal of solid-state circuits Vol. 23; no. 5; pp. 1176 - 1181
Main Authors Boudon, G., Mollier, P., Nuez, J.-P., Wallart, F., Bhattacharyya, A., Ogura, S.
Format Journal Article
LanguageEnglish
Published IEEE 01.10.1988
Subjects
CMOS logic circuits
CMOS technology
Computer aided instruction
Delay
FETs
Prototypes
Silicides
Space technology
Titanium
Voltage
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Summary:A 20 K NAND2 equivalent CMOS gate array prototype with 0.5- mu m channel length FETs is described. The 7.5*7.5-mm chip is designed for high performance with 200-ps gate delay. Large macros such as a 32-b RISC (reduced instruction-set computer) processor and 128*8 SRAM (static random-access memory) have been implemented with automatic placement and wiring tools. Their respective predicted performances of 17-ns cycle and 6.1-ns access time have been verified. This confirms that the speed of complex functions in half-micrometer-channel-length CMOS technology is getting close to the speed achieved by current bipolar hardware.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9200
1558-173X
DOI:10.1109/4.5941