Logic-I/O Threshold Comparing -Dosimeter in Radiation Insensitive Deep-Sub-Micron CMOS

• Published in: IEEE transactions on nuclear science Vol. 63; no. 2; pp. 1247 - 1250
• Main Authors: Tang, Adrian, Kim, Yangyho, Chang, Mau-Chung Frank
• Format: Journal Article
• Language: English
• Published: New York The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 01.04.2016
• ISSN: 0018-9499; 1558-1578
• DOI: 10.1109/TNS.2016.2528219

This paper discusses challenges of implementing embedded dosimeters into larger CMOS systems-on-chip (SoCs) in deep-scaled CMOS technologies (with gate lengths smaller than 90 nm) where the high level of intrinsic radiation hardness and limited availability of floating gate structures prohibit realizing a highly sensitive radfet-type dosimeter. We therefore propose a novel Logic-I/O Threshold Comparison Dosimeter, which offers compatibility with advanced CMOS technology nodes and co-integration with other circuitry. The proposed dosimeter estimates dose level by directly comparing threshold voltages between I/O and logic devices. Furthermore, through carefully sizing the logic and I/O devices and designing the vital comparator circuitry, we can also achieve required temperature independence for deep-space applications. A prototype is then fabricated in 65-nm CMOS, and measured up to 75 Mrad(Si) of total ionized dose at a Cobalt 60 ([Formula Omitted]) facility.