PERFORMANCE PARAMETERS OF LOW POWER SRAM CELLS: A REVIEW

In this paper various Low Power SRAM cell design techniques have been reviewed on the bases of power, stability and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell has fastest in speed but at low supply voltage stability...

Full description

Saved in:
Bibliographic Details
Published inI-Manager's Journal on Circuits & Systems Vol. 6; no. 1; p. 25
Main Authors NIDHI, TIWARI, VAIBHAV, NEEMA, KAMAL, J RANGRA, YOGESH, CHANDRA SHARMA
Format Journal Article
LanguageEnglish
Published Nagercoil iManager Publications 2018
Subjects
Computer architecture
Computer memory
Design
Design parameters
Electric potential
Integrated circuits
Machine learning
Network interface cards
Product development
Static random access memory
Surgical implants
Very large scale integration
Voltage stability
Online AccessGet full text

Cover

More Information
Summary:In this paper various Low Power SRAM cell design techniques have been reviewed on the bases of power, stability and delay. Many studies have proposed various SRAM architectures for different applications. It has been reported that 6T SRAM cell has fastest in speed but at low supply voltage stability is a critical issue for 6T SRAM cell. It is found that 8T SRAM cell shows the highest level of stability at Low supply voltage but it has area penalty. Hence in this work all the required performance parameters of various SRAM cell architectures have been reviewed. This work will be helpful for VLSI designer to choose proper memory architecture as per applications. For example machine learning need high performance memory block while biomedical implants require low power memory block. This paper also presents various tradeoffs between various design parameters of SRAM.
ISSN:2321-7502
2322-035X
DOI:10.26634/jcir.6.1.14495