VLSI Implementation of CMOS Full Adders with Low Leakage Power

• Published in: International journal of computer network and information security Vol. 10; no. 4; pp. 20 - 27
• Main Authors: B S, Manisha, S B, Rudraswamy
• Format: Journal Article
• Language: English
• Published: Hong Kong Modern Education and Computer Science Press 08.04.2018
• Subjects: CMOS; Integrated circuits; Semiconductor devices; Technology assessment; Transistors; Very large scale integration
• ISSN: 2074-9090; 2074-9104
• DOI: 10.5815/ijcnis.2018.04.03

In this paper, we present two different methods to implement 1-bit full adder namely MTJ based full adder design also called MFA and Lector method based full adder design. These adders are designed and implemented using CADENCE Design Suite 6.1.6 Virtuoso ADE. The implemented design is verified using CADENCE ASSURA. The performance is measured for 45nm technology and a comparative analysis of transistor count; delay and power of the adders were performed. When compared with the previous MFA the proposed MFA overcomes the SEU error which is a result of body biasing. In Lector technique the transistor density is reduced by implementing the sum logic in terms of carry thus reducing the area. In order to attain the complete logic levels buffers are introduced at the sum and carry outputs of both Lector and MFA. The Lector method uses less number of transistors when compared with proposed MFA, but the proposed MFA is efficient because it achieves minimum power dissipation when compared to the Lector method.