A 0.33-V, 500-kHz, 3.94- \mu\hbox 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 59; no. 12; pp. 863 - 867
• Main Authors: Lu, Chien-Yu, Tu, Ming-Hsien, Yang, Hao-I, Wu, Ya-Ping, Huang, Huan-Shun, Lin, Yuh-Jiun, Lee, Kuen-Di, Kao, Yung-Shin, Chuang, Ching-Te, Jou, Shyh-Jye, Hwang, Wei
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2012
• Subjects: 9T SRAM cell; CMOS integrated circuits; CMOS technology; Computer architecture; Low voltage; Microprocessors; Negative bit-line (NBL); Random access memory; ripple bit-line (RPBL); Solid state circuits; subthreshold static random-access memory (SRAM); ultra-low voltage
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2012.2231017

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 × 385 μm 2 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 °C. The measured total power consumption is 3.94 μW at 0.33 V, 500 kHz, and 25 °C .