A 47 \,\times\, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 45; no. 12; pp. 2828 - 2837
• Main Authors: O'Mahony, Frank, Jaussi, James E, Kennedy, Joseph, Balamurugan, Ganesh, Mansuri, Mozhgan, Roberts, Clark, Shekhar, Sudip, Mooney, R, Casper, Bryan
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2010
• Subjects: Bandwidth; Driver circuits; I/O; Integrated circuit interconnections; interface; link; low area; low power; Power demand; power management; power states; Receivers; standby; transceiver; Transceivers; Transmitters
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2010.2076214

A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in <;5 ns. The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10 -18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm 2 active silicon area.