A 64 \times 64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers

• Published in: IEEE journal of solid-state circuits Vol. 43; no. 9; pp. 1940 - 1950
• Main Authors: Berger, R., Rathman, D.D., Tyrrell, B.M., Kohler, E.J., Rose, M.K., Murphy, R.A., Perry, T.S., Robey, H.F., Weber, F.A., Craig, D.M., Soares, A.M., Vernon, S.P., Reich, R.K.
• Format: Journal Article
• Language: English
• Published: IEEE 01.09.2008
• Subjects: Circuit testing; Clocks; CMOS readout; CMOS technology; current steering circuit; Dynamic range; H-tree clock distribution; high-speed imaging; integrated circuit design; Jitter; Photodiodes; Silicon; snapshot exposures; X-ray detection; X-ray detectors; X-ray imaging
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2008.2001912

A 64 times 64-pixel test circuit was designed and fabricated in 0.18-mum CMOS technology for investigating high-speed imaging with large-format imagers. Several features are integrated into the circuit architecture to achieve fast exposure times with low-skew and jitter for simultaneous pixel snapshots. These features include an H-tree clock distribution with local and global repeaters, single-edge trigger propagation, local exposure control, and current-steering sampling circuits. To evaluate the circuit performance, test structures are periodically located throughout the 64 times 64-pixel device. Measured devices have exposure times that can be varied between 75 ps to 305 ps with skew times for all pixels less than plusmn 3 ps and jitter that is less than plusmn1.2 ps rms. Other performance characteristics are a readout noise of approximately 115 e- rms and an upper dynamic range of 310,000 e-.