A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4\times Faster Clock Frequency and > 6\times Higher Restore Speed

With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed ba...

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Published inIEEE journal of solid-state circuits Vol. 52; no. 10; pp. 2769 - 2785
Main Authors Zhibo Wang, Yongpan Liu, Lee, Albert, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong-Jung Lin, Khalili Amiri, Pedram, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang
Format Journal Article
LanguageEnglish
Published IEEE 01.10.2017
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Abstract With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6× and >6000× higher speed and energy efficiency of restore and >4× faster operating frequency compared with that of state of the art.
AbstractList With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well as "normally off" applications. Recently, zero-standby power and fast switching nonvolatile processors (NVPs) have been proposed based on emerging nonvolatile memories (NVMs), such as ferroelectric RAM or spin-transfer-torque magnetic RAM. However, previous NVPs store all data to NVM upon every power interruption, resulting in high-energy consumption and degraded NVM endurance. This paper presents a 65-nm fully CMOS-logic-compatible ReRAM-based NVP supporting time-space domain adaption. It incorporates adaptive nonvolatile controller, nonvolatile flip-flops, and nonvolatile static random access memory (nvSRAM) with self-write termination. Data redundancy in both time and space domain is fully exploited to reduce store/restore time/energy and boost clock frequency. The NVP operates at >100 MHz and achieves 20 ns/0.45 nJ restore time/energy, realizing >6× and >6000× higher speed and energy efficiency of restore and >4× faster operating frequency compared with that of state of the art.
Author Huazhong Yang
Ya-Chin King
Zhibo Wang
Wei-En Lin
Zhe Yuan
Jinyang Li
Chieh-Pu Lo
Lee, Albert
Wei-Hao Chen
Meng-Fan Chang
Chrong-Jung Lin
Fang Su
Hsiao-Yun Chiu
Khalili Amiri, Pedram
Kang-Lung Wang
Yongpan Liu
Chien-Chen Lin
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Snippet With an ever-increasing demand for energy efficiency, processors with instant-on and zero leakage features are highly appreciated in energy harvesting as well...
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SubjectTerms Aerospace electronics
Computer architecture
Monitoring
nonvolatile flip-flops (nvFF)
Nonvolatile memory
Nonvolatile processor (NVP)
nonvolatile SRAM (nvSRAM)
Random access memory
Registers
self-write termination (SWT)
Time-domain analysis
time-space domain adaption
Title A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4\times Faster Clock Frequency and > 6\times Higher Restore Speed
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