A 20 Gb/s 1:4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 \mu} CMOS Technology
In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing ma...
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Published in | IEEE journal of solid-state circuits Vol. 43; no. 2; pp. 541 - 549 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
IEEE
01.02.2008
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Subjects | |
Online Access | Get full text |
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Summary: | In this paper, a 20 Gb/s 1:4 DEMUX without inductors is presented. A coupled latch with shared current source and buffer insertion scheme improves the signal bandwidth. A divide-by-2 circuit with a static frequency divider and a delay-locked loop achieves low power consumption and enhanced timing margin without the degradation of the divider sensitivity. A horizontal eye opening is 71.3%, and a vertical eye opening is 52%. The test chip fabricated in a 0.13 mum process consumes 210 mW from 1.2 V logic supply. |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/JSSC.2007.914332 |