InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and I/I Ratio Near \hbox

• Published in: IEEE electron device letters Vol. 33; no. 6; pp. 782 - 784
• Main Authors: Guangle Zhou, Yeqing Lu, Rui Li, Qin Zhang, Qingmin Liu, Vasen, T., Haijun Zhu, Jenn-Ming Kuo, Kosel, T., Wistey, M., Fay, P., Seabaugh, A., Huili Xing
• Format: Journal Article
• Language: English
• Published: IEEE 01.06.2012
• Subjects: FETs; Heterojunction; Indium gallium arsenide; Indium phosphide; InGaAs; InP; Logic gates; metal-oxide-semiconductor field-effect transistors (MOSFETs); nanoelectronics; Passivation; subthreshold swing; transistors; tunnel field-effect transistor (TFET); Tunneling
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2012.2189546

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In ∞=0.53->;1 GaAs/p + InP heterojunction have been demonstrated to exhibit simultaneously a high I ON /I OFF ratio of 6 × 10 5 , a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at V DS = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN ∞ mesa passivation to preserve the integrity of the thin exposed semiconductor layers.