A Fully Integrated 4 \times 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 \mu} CMOS SOI Technology

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 12; pp. 2736 - 2744
• Main Authors: Narasimha, A., Analui, B., Liang, Y., Sleboda, T.J., Abdalla, S., Balmater, E., Gloeckner, S., Guckenberger, D., Harrison, M., Koumans, R.G.M.P., Kucharski, D., Mekis, A., Mirsaidi, S., Dan Song, Pinguet, T.
• Format: Journal Article
• Language: English
• Published: IEEE 01.12.2007
• Subjects: CMOS optoelectronic transceiver; CMOS technology; Costs; high-speed integrated circuits; integrated optical interleaver; Integrated optics; Optical attenuators; Optical devices; Optical receivers; Optical transmitters; photonic integrated circuits; Silicon; silicon photonics; Transceivers; Wavelength division multiplexing
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2007.908713

Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s was achieved over a single fiber, with a BER of less than 10 -12 and a power consumption of 3.5 W.