Improving 64-Bit Java IPF Performance by Compressing Heap References

64-bit processor architectures like the Intel® Itanium®Processor Family are designed for large applicationsthat need large memory addresses.When runningapplications that fit within a 32-bit address space, 64-bitCPUs are at a disadvantage compared to 32-bit CPUsbecause of the larger memory footprints...

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Published inCode Generation and Optimization: Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization; 20-24 Mar. 2004 p. 100
Main Authors Adl-Tabatabai, Ali-Reza, Bharadwaj, Jay, Cierniak, Michal, Eng, Marsha, Fang, Jesse, Lewis, Brian T., Murphy, Brian R., Stichnoth, James M.
Format Conference Proceeding
LanguageEnglish
Published Washington, DC, USA IEEE Computer Society 20.03.2004
SeriesACM Conferences
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Summary:64-bit processor architectures like the Intel® Itanium®Processor Family are designed for large applicationsthat need large memory addresses.When runningapplications that fit within a 32-bit address space, 64-bitCPUs are at a disadvantage compared to 32-bit CPUsbecause of the larger memory footprints for their data.This results in worse cache and TLB utilization, and consequentlylower performance because of increased missratios.This paper considers software techniques for virtualmachines that allow 32-bit pointers to be used on 64-bitCPUs for managed runtime applications that do notneed the full 64-bit address space.We describe ourpointer compression techniques and discuss our experienceimplementating these for Java1 applications.In addition,we give performance results with our techniques forboth the SPEC JVM98 and SPEC JBB2000 benchmarks.We demonstrate a 12% performance improvement onSPEC JBB2000 and a reduction in the number of garbagecollections required for a given heap size.
Bibliography:SourceType-Conference Papers & Proceedings-1
ObjectType-Conference Paper-1
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ISBN:0769521029
9780769521022
DOI:10.5555/977395.977662