Power minization in LUT-based FPGA technology mapping

• Published in: Proceedings of the 2001 Asia and South Pacific Design Automation Conference pp. 635 - 640
• Main Authors: Wang, Zhi-Hong, Liu, En-Cheng, Lai, Jianbang, Wang, Ting-Chi
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 30.01.2001
• Series: ACM Conferences
• Subjects: Applied computing > Physical sciences and engineering > Electronics; Hardware > Integrated circuits > Logic circuits > Combinational circuits; Hardware > Robustness; Hardware > Very large scale integration design > Application-specific VLSI designs
• ISBN: 0780366344; 9780780366343
• DOI: 10.1145/370155.370569

In this paper, we consider the problem of lookup table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results indicate that our algorithm reduces the average power consumption by up to 14.18%, and the average number of LUTs by up to 6.99% over an existing method.