Low load latency through sum-addressed memory (SAM)

• Published in: Proceedings of the 25th annual international symposium on Computer architecture pp. 369 - 379
• Main Authors: Lynch, William L., Lauterbach, Gary, Chamdani, Joseph I.
• Format: Conference Proceeding
• Language: English
• Published: Washington, DC, USA IEEE Computer Society 16.04.1998
• Series: ACM Conferences
• Subjects: Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data; General and reference > Cross-computing tools and techniques > Design
• ISBN: 9780818684913; 0818684917
• DOI: 10.1145/279358.279406

Load latency contributes significantly to execution time. Because most cache accesses hit, cache-hit latency becomes an important component of expected load latency. Most modern microprocessors have base+offset addressing loads; thus effective cache-hit latency includes an addition as well as the RAM access.This paper introduces a new technique used in the UltraSPARC III microprocessor, Sum-Addressed Memory (SAM), which performs true addition using the decoder of the RAM array, with very low latency. We compare SAM with other methods for reducing the add part of load latency. These methods include sum-prediction with recovery, and bitwise indexing with duplicate-tolerance. The results demonstrate the superior performance of SAM.