20 ps Time Resolution with a Fully-Efficient Monolithic Silicon Pixel Detector without Internal Gain Layer

• Published in: arXiv.org
• Main Authors: Zambito, S, Milanesio, M, Moretti, T, Paolozzi, L, Munker, M, Cardella, R, Kugathasan, T, Martinelli, F, Picardi, A, Elviretti, M, Rücker, H, Trusch, A, Cadoux, F, Cardarelli, R, Débieux, S, Favre, Y, Fenoglio, C A, Ferrere, D, Gonzalez-Sevilla, S, Iodice, L, Kotitsa, R, Magliocca, C, Nessi, M, Pizarro-Medina, A, J Sabater Iglesias, Saidi, J, M Vicente Barreto Pinto, Iacobucci, G
• Format: Paper Journal Article
• Language: English
• Published: Ithaca Cornell University Library, arXiv.org 28.01.2023
• Subjects: Design optimization; Electronics; Physics - Instrumentation and Detectors; Pixels; Prototypes
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.2301.12244

A second monolithic silicon pixel prototype was produced for the MONOLITH project. The ASIC contains a matrix of hexagonal pixels with 100 {\mu}m pitch, readout by a low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 {\mu}m thick epilayer of 350 {\Omega}cm resistivity were used to produce a fully depleted sensor. Laboratory and testbeam measurements of the analog channels present in the pixel matrix show that the sensor has a 130 V wide bias-voltage operation plateau at which the efficiency is 99.8%. Although this prototype does not include an internal gain layer, the design optimised for timing of the sensor and the front-end electronics provides a time resolutions of 20 ps.