DMR-based Technique for Fault Tolerant AES S-box Architecture

This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. If a transient natural or even malicious fault in each pipeline stage is detected, the corresponding error signal becomes high and as a result, the control unit holds the output of our propose...

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Bibliographic Details
Main Authors Taheri, Mahdi, Sheikhpour, Saeideh, Ansari, Mohammad Saeed, Mahani, Ali
Format Journal Article
LanguageEnglish
Published 11.09.2020
Subjects
Computer Science - Hardware Architecture
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Summary:This paper presents a high-throughput fault-resilient hardware implementation of AES S-box, called HFS-box. If a transient natural or even malicious fault in each pipeline stage is detected, the corresponding error signal becomes high and as a result, the control unit holds the output of our proposed DMR voter till the fault effect disappears. The proposed low-cost HFS-box provides a high capability of fault-tolerant against transient faults with any duration by putting low area overhead, i.e. 137%, and low throughput degradation, i.e. 11.3%, on the original implementation.
DOI:10.48550/arxiv.2009.05329