56 Gbps PCB Design Strategies for Clean, Low-Skew Channels
Although next generation (>28 Gbps) SerDes standards have been contemplated for several years, it has not been clear whether PCB structures supporting 56 Gbps NRZ will be feasible and practical. In this paper, we assess a number of specific PCB design strategies (related to pin-field breakouts, v...
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Main Authors | , , , |
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Format | Journal Article |
Language | English |
Published |
17.01.2023
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Subjects | |
Online Access | Get full text |
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Summary: | Although next generation (>28 Gbps) SerDes standards have been contemplated
for several years, it has not been clear whether PCB structures supporting 56
Gbps NRZ will be feasible and practical. In this paper, we assess a number of
specific PCB design strategies (related to pin-field breakouts, via stubs, and
fiber weave skew) both through simulation and through measurement of a wide
range of structures on a PCB test vehicle. We demonstrate that conventional
approaches in many cases will not be sufficient, but that modest
(manufacturable) design changes can enable low-skew 56 Gbps NRZ channels having
acceptable insertion and return loss. |
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DOI: | 10.48550/arxiv.2304.01909 |