PIUMA: Programmable Integrated Unified Memory Architecture
High performance large scale graph analytics is essential to timely analyze relationships in big data sets. Conventional processor architectures suffer from inefficient resource usage and bad scaling on graph workloads. To enable efficient and scalable graph analysis, Intel developed the Programmabl...
Saved in:
Main Authors | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
---|---|
Format | Journal Article |
Language | English |
Published |
13.10.2020
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | High performance large scale graph analytics is essential to timely analyze
relationships in big data sets. Conventional processor architectures suffer
from inefficient resource usage and bad scaling on graph workloads. To enable
efficient and scalable graph analysis, Intel developed the Programmable
Integrated Unified Memory Architecture (PIUMA). PIUMA consists of many
multi-threaded cores, fine-grained memory and network accesses, a globally
shared address space and powerful offload engines. This paper presents the
PIUMA architecture, and provides initial performance estimations, projecting
that a PIUMA node will outperform a conventional compute node by one to two
orders of magnitude. Furthermore, PIUMA continues to scale across multiple
nodes, which is a challenge in conventional multinode setups. |
---|---|
DOI: | 10.48550/arxiv.2010.06277 |