A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design

The BCD (Binary Coded Decimal) being the more accurate and human-readable representation with ease of conversion, is prevailing in the computing and electronic communication.In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity. BCD adder is mo...

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Bibliographic Details
Main Authors Sworna, Zarrin Tasnim, Haque, Mubin Ul, Babu, Hafiz Md. Hasan, Jamal, Lafifa
Format Journal Article
LanguageEnglish
Published 17.03.2022
Subjects
Computer Science - Hardware Architecture
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Summary:The BCD (Binary Coded Decimal) being the more accurate and human-readable representation with ease of conversion, is prevailing in the computing and electronic communication.In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity. BCD adder is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology's enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper.
DOI:10.48550/arxiv.2203.09665