FPGA Technology Mapping Using Sketch-Guided Program Synthesis

• Published in: arXiv.org
• Main Authors: Smith, Gus Henry, Kushigian, Ben, Canumalla, Vishal, Cheung, Andrew, Lyubomirsky, Steven, Porncharoenwase, Sorawee, Just, René, Bernstein, Gilbert Louis, Tatlock, Zachary
• Format: Paper Journal Article
• Language: English
• Published: Ithaca Cornell University Library, arXiv.org 29.01.2024
• Subjects: Computer architecture; Computer Science - Hardware Architecture; Computer Science - Programming Languages; Digital signal processing; Digital signal processors; Handwriting; Hardware; Mapping; Semantics; State of the art; Synthesis
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.2401.16526

FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecture-specific primitives of the target FPGA. As FPGAs become increasingly heterogeneous, achieving high performance requires hardware synthesis tools that better support mapping to complex, highly configurable primitives like digital signal processors (DSPs). Current tools support DSP mapping via handwritten special-case mapping rules, which are laborious to write, error-prone, and often overlook mapping opportunities. We introduce Lakeroad, a principled approach to technology mapping via sketch-guided program synthesis. Lakeroad leverages two techniques -- architecture-independent sketch templates and semantics extraction from HDL -- to provide extensible technology mapping with stronger correctness guarantees and higher coverage of mapping opportunities than state-of-the-art tools. Across representative microbenchmarks, Lakeroad produces 2--3.5\(\times\) the number of optimal mappings compared to proprietary state-of-the-art tools and 6--44\(\times\) the number of optimal mappings compared to popular open-source tools, while also providing correctness guarantees not given by any other tool.