Robust and accurate fine-grain power models for embedded systems with no on-chip PMU

• Published in: arXiv.org
• Main Authors: Nikov, Kris, Martinez, Marcos, Wegener, Simon, Nunez-Yanez, Jose, Chamski, Zbigniew, Georgiou, Kyriakos, Eder, Kerstin
• Format: Paper Journal Article
• Language: English
• Published: Ithaca Cornell University Library, arXiv.org 09.11.2021
• Subjects: Central processing units; Computer Science - Distributed, Parallel, and Cluster Computing; CPUs; Data collection; Embedded systems; Fault tolerance; Field programmable gate arrays; Industrial applications; Microprocessors; Platforms; Robustness
• ISSN: 2331-8422
• DOI: 10.48550/arxiv.2106.00565

This paper presents a novel approach to event-based power modelling for embedded platforms that do not have a Performance Monitoring Unit (PMU). The method involves complementing the target hardware platform, where the physical power data is measured, with another platform on which the CPU performance data, that is needed for model generation, can be collected. The methodology is used to generate accurate fine-grain power models for the the Gaisler GR712RC dual-core LEON3 fault-tolerant SPARC processor with on-board power sensors and no PMU. A Kintex UltraScale FPGA is used as the support platform to obtain the required CPU performance data, by running a soft-core representation of the dual-core LEON3 as on the GR712RC but with a PMU implementation. Both platforms execute the same benchmark set and data collection is synchronised using per-sample timestamps so that the power sensor data from the GR712RC board can be matched to the PMU data from the FPGA. The synchronised samples are then processed by the Robust Energy and Power Predictor Selection (REPPS) software in order to generate power models. The models achieve less than 2% power estimation error when validated on an industrial use-case and can successfully follow program phases, which makes them suitable for runtime power profiling.