Single InAs/GaSb Nanowire Low-Power CMOS Inverter

• Published in: Nano letters Vol. 12; no. 11; pp. 5593 - 5597
• Main Authors: Dey, Anil W, Svensson, Johannes, Borg, B. Mattias, Ek, Martin, Wernersson, Lars-Erik
• Format: Journal Article
• Language: English
• Published: Washington, DC American Chemical Society 14.11.2012
• Subjects: Applied sciences; Cross-disciplinary physics: materials science; rheology; Devices; Electronics; Engineering and Technology; Exact sciences and technology; Heterostructures; III-V CMOS; InAs/GaSb; inverter; Inverters; Logic; low-power operation; Materials science; Molecular electronics, nanoelectronics; Nano Technology; Nanocrystalline materials; Nanoscale materials and structures: fabrication and characterization; Nanoteknik; Nanowire; Nanowires; Physics; Quantum wires; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Swing; Teknik; Transistors; Nanowire; inverter; III-V CMOS; InAs/GaSb; low-power operation; Buffer layer; Gallium antimonides; Transport properties; Hole mobility; n channel; Inverters; Indium arsenides; III-V compound; Wave forms; Capacitance; Nanowires; Transistors; Nanostructured materials; Heterostructures; III-V semiconductors
• ISSN: 1530-6984; 1530-6992; 1530-6992
• DOI: 10.1021/nl302658y

III–V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III–V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal–oxide–semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III–V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V ds = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.