Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

• Published in: VLSI Design Vol. 2014; no. 2014; pp. 73 - 85
• Main Authors: Bailey, Christopher, Mullane, Brendan
• Format: Journal Article
• Language: English
• Published: New York Hindawi Limiteds 01.01.2014; Hindawi Publishing Corporation; Hindawi Limited
• Subjects: Arrays; Colleges & universities; Computer simulation; Delay; Density; Extraction; Nanostructure; Semiconductors; Stacks; Very large scale integration
• ISSN: 1065-514X; 1563-5171
• DOI: 10.1155/2014/493189

Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA). We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.