An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories
In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes...
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Published in | Design, Automation and Test in Europe pp. 592 - 597 |
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Main Authors | , , , , |
Format | Conference Proceeding |
Language | English |
Published |
Washington, DC, USA
IEEE Computer Society
07.03.2005
IEEE |
Series | ACM Conferences |
Subjects | |
Online Access | Get full text |
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Summary: | In this paper we propose a new Built in Current Sensor (BICS) to detect single event upsets in SRAM. The BICS is designed and validated for 100nm process technology. The BICS reliability analysis for process, voltage, temperature, and power supply noise are provided. This BICS detect various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. This BICS found to be very reliable for process, voltage and temperature variation and under stringent noise conditions. |
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Bibliography: | SourceType-Conference Papers & Proceedings-1 ObjectType-Conference Paper-1 content type line 25 |
ISBN: | 9780769522883 0769522882 |
ISSN: | 1530-1591 1558-1101 |
DOI: | 10.1109/DATE.2005.54 |