Performance-constrained worst-case variability minimization of VLSI circuits

• Published in: 30th ACM/IEEE Design Automation Conference pp. 154 - 158
• Main Authors: Dharchoudhury, A., Kang, S. M.
• Format: Conference Proceeding
• Language: English
• Published: New York, NY, USA ACM 01.07.1993
• Series: ACM Conferences
• Subjects: BiCMOS integrated circuits; Clocks; Fluctuations; Hardware > Hardware validation > Functional verification > Simulation and emulation; Hardware > Integrated circuits; Hardware > Very large scale integration design; Minimization; Performance evaluation; Response surface methodology; Semiconductor device modeling; Temperature; Very large scale integration; Voltage
• ISBN: 9780897915779; 0897915771
• ISSN: 0738-100X
• DOI: 10.1145/157485.164647

This paper describes a new technique to design circuits such that the variability of the circuit performances due to device parameter fluctuations meets specifications for all values of the environmental parameters (such as operating temperature or voltage supply). The worst-case value of the performance variability is minimized and specifications on the nominal value of the performance measure are handled simultaneously. Response surface models are used to provide efficient and accurate estimates for the performance values and variability during the optimization. This technique has been successfully applied to significantly increase the parametric yields of a BiCMOS voltage-to-current converter circuit and a CMOS clock driver circuit.